VLSI Implementation of Self Time Adder using Recursive Approach

Authors:SALEENDRA LAKSHMIKANTH, B.PRATHAP REDDY

0612-0615

Design and Analysis of Low-Power and Area-Efficient Shift Register Using Pulsed Latches

Authors:Y.VEDAVATHI, P.SAMULU

0616-0620

An Efficient Soc Design for JVT & ME using BIST Techniques

Authors:S M DIMPLE RATHOD, G.ARUNA KUMARI

0621-0631

A Low CMOS Voltage Differential Logic Style with Supply Voltage Approaching Device Threshold

Authors:S. PADMAJA BAI, V. DAMODAR

0632-0641

An Efficient High Speed Low Power Quantum-Dot Cellular Automata Adders

Authors:SREE SATYA, C. KUMARA NARAYANA SWAMY

0642-0647

An Efficient Design & Implementation of Fir Filter on Wallace Tree Multiplier for Low Power and High Speed Operations

Authors:FAYAZ AHAMMAD, RAGHAVENDRA S

0648-0654

An Efficient Multifunction Residue Architecture for Cryptography

Authors:N. V. DIVYA, G. VISWANATH

0655-0658

Design of Power Efficient High Performance SRAM Cell using Transmission Gates

Authors:J. RAMESH, P. BRUNDAVANI

0659-0663